1. Field of Invention
This invention relates to power control and, more particularly, to moderating the application of power to electronic circuitry.
2. Description of Related Art
Electronic systems are frequently comprised of several modules, each drawing AC power from a common source. Furthermore, power supplies used in electronic equipment characteristically demand a high momentary current at startup. Therefore, switching on all of the modules simultaneously can result in a substantial combined startup current. Excessive transient currents associated with such a concurrent startup can induce strong magnetic fields or voltage spikes that may overstress electronic devices, causing them to fail.
High cumulative startup current arising from simultaneous activation of multiple devices is often a problem in rack-mounted electronic test systems. Such systems typically consist of several electronic test equipment and instruments that are mounted together in an equipment rack and plugged into the same AC power source. The rack generally has a single master power switch; when the switch is closed, all of the equipment in the rack is activated at once. (Note that the power coming back on line following a power outage can also produce the same transient as turning on the power switch.) Since the startup currents, also known as inrush startup currents, are additive, the combined transient current may be high enough to cause damage.
A further example of this problem may be the distributed power supply within a personal computer. The central processor in modern personal computers has grown tremendously in terms of operating speed and processing power. However, increased complexity and greater current consumption have accompanied improvements in performance. The CPU used in the original IBM Personal Computer contained a mere 29,000 transistors, ran at a clock speed of only 5 MHz, and required only 0.05 Amperes of operating current. A present day CPU, such as the AMD Athlon processor, may contain 22 million transistors, run at a clock speed of more than 1 GHz, and consume over 35 Amperes of current. The computer power supply must support not only the CPU, but disk drives, peripheral circuit cards, peripheral modules, etc. When the computer is first switched on, the simultaneous imposition of these various loads burdens the power supply to supply huge inrush currents that cause large magnetic fields and large voltage spikes. The electromagnetic fields associated with large transient currents may also interfere with the initialization of the system.
It is common practice to include protective devices such as surge arrestors and soft-start circuitry in electronic power supplies. Such devices have limited effectiveness in mitigating the effects of line voltage surges, and reducing the magnitude of startup currents. Despite these measures, the peak startup current will often be significantly higher than the rated steady state current of the power supply. As discussed above, the combined startup currents of multiple power supplies may be high enough to induce electromagnetic effects; such phenomena can interfere with the power supply or supported circuitry, and are not amenable to surge arrestors and the like. Furthermore, these collective startup currents may severely overload the power mains and associated switching components.
Connected with reliability issues, such as those discussed above, are cost concerns. Power components that must be subjected to concurrent startup currents are of necessity overbuilt. The design engineer""s traditional xe2x80x9cworst casexe2x80x9d criterion dictates that device tolerances be sufficient to avoid failure with startup current demands that may be far in excess of the nominal operating conditions. Unfortunately, larger transformers, heavier switch contacts, etc. are typically costlier. Added expense is associated with circuits to supply large inrush currents and output modules to withstand voltage and magnetic surges. Thus, the need to tolerate simultaneous startup currents drives up the cost of the power distribution components.
In view of the above-mentioned problems, it would be beneficial to have an automatic system for applying power to multiple loads that avoids simultaneous startup currents. The system should be capable of performing an orderly restart in the event of power loss and recovery. It would be advantageous if the system were capable of operating with either an AC or a DC-based power source. Moreover, the system should be inexpensive and readily adaptable to perform power sequencing in a variety of different applications, e.g., computer peripherals, test equipment racks, automated production lines.
The problems outlined above are in large part solved by a power sequencing system and method. The system described herein sequentially connects multiple loads to a main power source, thereby distributing the startup current over time and minimizing the possibility of component stress and interference associated with surge currents. It operates during either an initial application of power, or the recovery of power following an outage. The system is simple and inexpensive, and lends itself to incorporation into a variety of products. Furthermore, it can be easily manufactured into an integrated circuit, or placed on the substrate of an existing IC as an on-chip peripheral device.
A power sequencer is contemplated, comprising a set of controllable power switching elements and associated circuitry for timing, signal distribution and control. The power switching elements receive, via the distribution circuitry, progressively delayed versions of a logic transition. The switching elements are thus activated by the circuitry in a timed sequence, and consecutively connect multiple loads to a power source. Since the loads are connected in stages, rather than simultaneously, the massive current associated with a combined startup is avoided. A further feature of the present design is the capability of series-connecting multiple power sequencers, such that each sequencer in the series is enabled only after its predecessor has completed its sequence. Assume, for example, that sequencers A and B each support 8 loads, and that B is enabled by A. When power is first applied, sequencer A successively connects its 8 loads to the power source at regular intervals. Until the 8th of sequencer A""s loads is connected, sequencer B remains inactive and its loads are isolated from the power source. When its 8th load is connected, sequencer A enables sequencer B, allowing it to begin sequentially connecting its 8 loads. In effect, the two series-connected sequencers behave as a single sequencer with a 16 load capacity. Arbitrarily many sequencers can be connected in this manner; each sequencer enables the next, and is itself enabled by the previous sequencer.
In an exemplary embodiment, the power sequencer comprises a logic-controlled timer and shift registers, which energize a set of relays that distribute power to multiple loads. The relays are actuated consecutively, at fixed intervals; thus, power is applied to the loads in stages, rather than all at once. This results in a much lower peak startup current than if the loads were brought up simultaneously. For example, in a test rack comprising 16 identical electrical loads, the power sequencer reduces the inrush current to {fraction (1/16)} what it would be if all the loads were energized at once. The logic controlling the startup sequence can be configured to operate in either a master or slave mode. In the master mode, the startup sequence begins as soon as the system is activated. In the slave mode, on the other hand, an enable input signal is required before sequencing can begin. This feature makes it possible to xe2x80x9cdaisy-chainxe2x80x9d multiple power sequencers, for use in situations involving a large number of loads, or where the loads are widely separated.
It should be noted that although a multi-load system can in some cases be brought on-line manually, so that power is sequentially applied to the loads, this does not safeguard the system against power outages. Current surges frequently take place when system power is abruptly restored following a power outage. All of the devices that were operating when the outage occurred simultaneously restart when the power returns, often resulting in a huge combined startup current. Thus, the mere practice of manually sequencing power to multiple loads does not protect against current surges.
The system described herein can be applied to both AC and DC power distribution, and may be advantageous in a variety of applications to minimize the cost of power supplies and input circuits, and reduce EMI emissions. It is inexpensive and scalable, and can easily be produced as a low-cost integrated circuit. Thus, it lends itself to inclusion as a value-added feature in products such as power strips.
In addition to the above-mentioned system, a method for implementing sequential application of power to multiple loads is contemplated herein. The method may comprise creating a sequence of voltage steps, wherein each voltage step in the sequence is delayed by a prescribed interval with respect to the previous steps. The progressively delayed series of voltage steps actuates power-switching components that, in turn, deliver power to the individual loads.